`timescale 1ns / 1ps
`define hp 50

module acautomaton_tb();
    reg clk;
    reg rst;
  {%- if M==1 %}
    wire match;
  {%- else %}
    wire [{{M-1}}:0] match;
  {%- endif %}
    reg [7:0] data;
    
    always #`hp clk = ~clk;
    
    initial begin
        clk = 0;
        rst = 0;
        #(`hp*10) rst = 1;
        #(`hp*5)  rst = 0;
        {%- for c in test_data %}
        @(negedge clk) data = "{{c}}";
        {%- endfor %}
        @(negedge clk) $stop();
    end
    
    acautomaton a0(
        .clk(clk),
        .rst(rst),
        .c(data),
        .match(match)
    );
endmodule